module adc_select(

	input		wire				clk_100m,
	input		wire				clk_50m,
	input		wire				clk_20m,
	input		wire				key_in,
	input		wire				ret_n,
	
	output	wire				adc_clk

);

	reg	adc_en;
	
	always @(posedge clk_50m or negedge ret_n)
		if(!ret_n)
			adc_en <= 1'b0;
		else if(key_in == 1'b1)
			adc_en <= ~adc_en;
		else 
			adc_en <= adc_en;

	assign adc_clk = (adc_en == 1'b0)? clk_100m : clk_20m;








endmodule 




























